Focal plane imaging sensors are well known for the purpose of acquiring an electronic image from a sensor array implemented on a semiconductor die. Particularly widely used such devices include the CMOS imaging array (hereafter, CMOS imager) and the charge coupled device (hereafter, CCD). It is known in prior art to remove material from the backside of substrates, particularly for CCD applications.
Focal plane imaging sensors can be backthinned for a number of reasons. Performance advantages of backthinned sensors can include improved light sensitivity as a result of improved effective fill factor. When properly passivated by a method such as that described in U.S. Pat. No. 5,688,715, backthinned CMOS sensors can demonstrate high sensitivity to both UV light and low energy (˜0.5 to 20 keV) electrons. This property of backthinned CMOS sensors makes them particularly suitable for use in vacuum tubes as a video based image intensifier. U.S. Pat. No. 6,285,018 B1 details the use of a backthinned CMOS sensor in an electron-bombarded configuration.
The application of primary interest is the embodiment where the backthinned CMOS sensor is mounted directly opposing a photocathode in a proximity-focused configuration as detailed in U.S. Pat. No. 6,285,018. When the described sensor is used as a night vision imager, images are often captured at very low signal levels.
There are many possible variations that may be used in the backside thinning process as applied to CMOS sensors. However, characteristics of CMOS sensors place them in a class that is distinct from CCDs thereby necessitating new procedures and manufacturing approaches. It has been found in practice that materials forming CMOS imagers from a range of manufacturers are all highly stressed mechanically, particularly in respect to the silicon layers of the device. This may result from the numerous metal and dielectric layers that characterize the modern CMOS imager. CCDs in contrast to CMOS imagers can be manufactured using only a couple metal layers and much thinner dielectric layers and possibly suffer a lesser degree of mechanical stress. Consequently, when CMOS die are thinned without a support structure bonded to the front side, the device curls and often breaks. As a result (apparently) of this residual stress, CMOS die require bonding (of the front or back surface of the device) to a support structure before thinning is carried out. This is a procedure common to both CMOS and CCD imaging devices. It is additionally believed that the level of stress found in CCDs is generally low enough to allow a device supported only by substrate around the periphery of the die to be thinned successfully, whereas comparable CMOS devices for such imaging applications generally fail if not supported over the front or back surface during thinning. A typical surface support material is Coming Code 7740/Pyrex glass. Typical bonding agents are thermal coefficient of expansion (TCE) matched frit glass for vacuum compatible assemblies or epoxy for less demanding applications. U.S. Pat. Nos. 6,168,965 and 6,169,319 describe a backside-illuminated sensor and method of manufacturing the same. These patents however result in a sensor that has a transparent substrate bonded to the backside surface. In order to be useful in the application of interest, the back surface of the sensor must remain exposed open. A method for forming a supported imager assembly suitable with the application of interest is detailed in U.S. Pat. No. 6,020,646.
Special care must be taken in the design of the CMOS die or the manufacturing process in order to avoid performance degradation of the CMOS die when it is packaged for backside illumination. Details of precautions required to minimize fixed pattern noise (FPN) degradation for example, are listed in a patent application Ser. No. 10/355,836, entitled Backthinned CMOS Sensor with Low Fixed Pattern Noise, filed simultaneously with the parent of this application, which is incorporated herein by reference. Degradation in the functionality of the CMOS sensor can also occur as a result of backside thinning. Most modern CMOS imagers include some sort of feedback loop to automatically set the black level on the output video. The analog voltage associated with true black is often obtained by reading out “Black Reference Pixels”. Black reference pixels are typically arrayed immediately next to the active image array. A metal layer shields the reference pixels in order to block any incoming light. Circuitry within the CMOS sensor then sets the voltage output by these reference pixels to yield, a low count or a user specified set point value that will typically be displayed as black. Cameras are traditionally set up to a black level set point that is slightly greater than the read noise. Camera gain is then set to achieve a suitable image. Proper black level set is especially important when working at very low signal levels, as is traditionally the case in the application of interest. If the black level is set too low, dim objects will be clipped and not displayed. If the black level is set too high, image contrast will suffer. When CMOS sensors are thinned via traditional methods, the backs of the black level reference pixels are exposed, as are the pixels in the active imaging array. Consequently, light and electrons incident upon the back of the die will induce signal in the reference pixels thereby voiding their value as black reference pixels.
In order to regain the benefit of black reference pixels on backside thinned CMOS die shielding of incident electrons (or photons) is required. One approach to such shielding, as described in U.S. Pat. No. 6,489,992, is to deposit a metal layer over the backside facing reference pixels, as typically used on the front side. However, in order to maintain a low dark current, characteristic of the dark current in the active array, either a special metalization is required (See U.S. Pat. No. 4,760,031) or a dopant profile must be specified on the backside surface before the metal is deposited (See U.S. Pat. No. 5,688,715). These processes however require a significant number of process steps to be performed on the die after the final light/electron-sensitive surface has been specified. These steps typically involve a photolithography step to define the deposition area. The added masking and handling steps can damage the sensitive surface thereby reducing device yield. Preserving the function of the black reference pixels, without added process steps is therefore desirable.
The target application for the invention is an electron bombarded CMOS imager such as described in U.S. Pat. No. 6,285,018 B1. Image intensifiers experience a modulation transfer function (MTF) degradation of sensor image associated with elastic scattering of electrons as the electrons strike the anode of the tube. In a proximity-focused tube the scattered (including backscattered) electrons will be attracted to, and re-impact the anode within a circle of radius equal to ˜2× the tube gap. This effect, often referred to as “halo”, is a particular problem when bright lights fall within the image intensifier field of view. There are a number of prior art approaches to minimize the impact of halo in image tubes incorporating a microchannel plate (MCP). U.S. Pat. No. 6,483,231 attempts to minimize halo in the cathode to MCP gap. U.S. Pat. No. 5,495,141 attempts to minimize halo in the MCP to screen gap. The collimator described in U.S. Pat. No. 5,495,141 may also be used in the target application. However, in a tube without a microchannel plate, the image flux electrons lost in the collimator will significantly reduce tube sensitivity. Other issues including tube complexity and the introduction of Moirè pattern associated with the interference of the hexagonally packed collimator and the square pixels of the CMOS sensor make this an inappropriate choice. Differences in the coefficient of expansion between the glass used to manufacture MCP-like structures and the silicon of CMOS die make it impossible to maintain pixel level alignments between a glass collimator and an electron bombarded active pixel imager over normal environmental temperature ranges. Modern dry etch technology is now capable of producing highly anisotropic etched structures in silicon. One method used to generate such structures is described in U.S. Pat. No. 5,501,893.
In modern image array sensors, pixel size is decreasing in line with the lower critical line width that can be held in modern fabrication facilities. The resolution of a backthinned sensor is a function of both pixel pitch and the thickness of the residual epitaxial material. In electron-bombarded backthinned sensors, the electrical charge is typically deposited proximate the back surface of the sensor as electron-hole pairs formed by energy loss of an incident energetic electron (or light quantum). The charge then follows a more or less random walk until it is captured in the charge collection node of a pixel. The random walk of diffusion results in resolution degradation in that charge deposited directly behind one pixel has some probability of diffusing to the charge collection node of a different pixel. As a general rule, the residual thickness of the epitaxy should be less than the pixel pitch to reduce this loss of resolution. The requirements on thickness uniformity increase as the image array thickness decreases. A second complication that occurs as a result of thinner arrays is a drop in the overall conductivity of the array. In backthinned image sensors, particularly those bound for gated applications, or electron bombarded applications where significant amounts of charge need to be transferred through the image array, voltage drops across the image array associated with low conductivity can present problems. Consequently, as pixel pitch decreases the thinning process becomes more demanding. Similarly, the passivation process, which results in a sheet of doped semiconductor at the back surface of the die, requires higher doping levels to maintain the desired conductivity and surface isolation properties. Thus passivation plays a dual role. It acts as a conductive plane behind the image plane and it “passivates” the surface, both lowering the collection of surface generated dark current and increasing the sensitivity to light and low energy electrons. As the residual epitaxial surface is thinned, electric fields from underlying pixels can interact with the passivation layer. This interaction can compensate some of the doping in the passivation layer making it less effective in its dual role. The net result of the thinning of the residual epitaxial thickness is to place increased demands on the thinning and passivation process or to lower device yield.
It is known in prior art (optically) illuminated image sensors to employ a doping gradient to minimize electron diffusion which would have the effect of degrading resolution through the lateral diffusion of electrons from a trajectory from the photon interaction site toward the nearest pixel. The slight electric field consequent to the doping gradient in such instance produces an acceleration in the direction of the gradient, that is, along the normal to the pixel array, reducing those random deviations in the electron trajectory which would terminate at pixels other than that pixel nearest the photon interaction site as described in U.S. Pat. No. 4,348,690.